DASIP 2023: Workshop on Design and Architectures for Signal and Image Processing
in conjunction with the 18th HiPEAC Conference in Toulouse, France, January 16-18, 2023.
DASIP 2023 will take place in conjunction with the 18th HiPEAC Conference in Toulouse, France, January 16-18, 2023
- Abstract registration November 4
- Submission deadline November 11
October 28, 2022
- Notification of acceptance December 16, 2022
- Camera ready papers January 7, 2023
The Workshop on Design and Architectures for Signal and Image Processing (DASIP) provides an inspiring international forum for the latest innovations and developments in the field of leading signal, image and video processing and machine learning in custom embedded, edge and cloud computing architectures and systems. The workshop program will include keynote speeches and contributed paper sessions.
Tuesday, January 17th
10:00 – 10:10 DASIP’23 Welcome and Opening
10:10 – 11:00 Keynote #1: Real-time 4K video stream processing on SoC FPGAs.
Tomasz Kryjak, AGH University of Science and Technology, Poland
The keynote will summarise the results of a 5-year research project on the hardware implementation of algorithms for processing 4K resolution video streams in real-time on SoC FPGAs (System on Chip Field Programmable Gate Arrays). First, the specifics of the 4K signal and the challenges of the so-called vector format (2 or 4 pixels per clock) will be presented. This will be followed by a discussion of the implemented modules and algorithms – from very basic point and context operations, to methods such as foreground object segmentation, optical flow, CLAHE (Contrast Limited Adaptive Histogram Equalization) filtering, ORB (Oriented FAST and Rotated BRIEF) feature point detection and matching, HOG+SVM (Histogram of Oriented Gradients + Support Vector Machine) pedestrian detection, object tracking (Siamese networks, correlation filters), connected component labeling and stereovision. In the final part of the presentation, the current research of the Embedded Vision Systems Team based at AGH University of Science and Technology in Krakow will be presented.
11:00 – 11:30 Coffee Break
11:30 – 13:00 Session #1: Methods and Applications I
Chair: Tiago M. Dias, ISEL – Técnico Lisboa
- 11:30 – 11:55 SCAPE: HW-Aware Clustering of Dataflow Actors for Tunable Scheduling Complexity.
Ophélie Renaud, Dylan Gageot, Karol Desnos and Jean-François Nezan.
- 11:55 – 12:20 Deep Recurrent Neural Network performing spectral recurrence on hyperspectral images for brain tissue classification.
Pedro L. Cebrián, Alberto Martín-Pérez, Manuel Villa, Jaime Sancho, Gonzalo Rosa, Guillermo Vazquez, Pallab Sutradhar, Alejandro Martinez de Ternero, Miguel Chavarrías, Alfonso Lagares, Eduardo Juarez and Cesar Sanz.
- 12:20 – 12.45 Brain blood vessel segmentation in hyperspectral images through linear operators.
Guillermo Vázquez, Manuel Villa, Alberto Martín-Pérez, Jaime Sancho, Gonzalo Rosa, Pedro L. Cebrián, Pallab Sutradhar, Alejandro Martinez de Ternero, Miguel Chavarrías, Alfonso Lagares, Eduardo Juarez and Cesar Sanz.
13:00 – 14:00 Lunch
14:00 – 15.30 Session #2: Hardware Architectures
Chair: Alfonso Rodríguez, Universidad Politécnica de Madrid, Spain
- 14:00 – 14:25 AINoC: new interconnect for future Deep Neural Network accelerators.
Hana Krichene, Rohit Prasad and Ayoub Mouhagir.
- 14:25 – 14:50 Real-time FPGA implementation of the Semi-Global Matching stereo vision algorithm for an 4K/UHD video stream.
Mariusz Grabowski and Tomasz Kryjak.
- 14:50 – 15:15 TaPaFuzz – An FPGA-Accelerated Framework for RISC-V IoT Graybox Fuzzing.
Florian Meisel, David Volz, Christoph Spang, Nguyen Tien Dat Tran and Andreas Koch.
15:30 – 16:00 Coffee Break
Wednesday, January 18th
10:10 – 11:00 Keynote #2: —Cancelled—
David González Arjona, GMV
11:00 – 11:30 Coffee Break
11:30 – 13:00 Session #3: Methods and Applications II
Chair: Karol Desnos, IETR – Institut National des Sciences Appliquées de Rennes, France
- 11:30 – 11:55 Adaptive Inference for FPGA-based 5G Automatic Modulation Classification.
Daniel de Oliveira Rubiano, Guilherme Korol and Antonio Carlos Schneider Beck.
- 11:55 – 12:20 High-Level Online Power Monitoring of FPGA IP Based on Machine Learning.
Majdi Richa, Jean-Christophe Prévotet, Mickaël Dardaillon, Mohamad Mroué and Abed Ellatif Samhat.
- 12:20 – 12:45 Neural Network Predictor for Fast Channel Change on DVB Set-Top-Boxes.
Tomás Malcata, Nuno Sebastião, Tiago Dias and Nuno Roma.
13:00 – 13:15 DASIP’23 Best Paper Award and Closing
The best paper award of the 16th edition of DASIP has been granted to “TaPaFuzz – An FPGA-Accelerated Framework for RISC-V IoT Graybox Fuzzing.” Florian Meisel, David Volz, Christoph Spang, Nguyen Tien Dat Tran and Andreas Koch.
Call for papers
List of topics
Prospective authors are invited to submit manuscripts on topics including, but not limited to:
Custom embedded, edge and cloud architectures and systems:
- Machine learning and deep learning architectures for inference and training
- Systems for autonomous vehicles : cars, drones, ships and space applications
- Image processing and compression architectures
- Smart cameras, security systems, behaviour recognition
- Edge and cloud processing: special routing, configurable co-processors and low energy considerations
- Real-time cryptography, secure computing, financial and personal data processing
- Computer arithmetic, approximate computing, probabilistic computing, nanocomputing, bio-inspired computing
- Biological data collection and analysis, bioinformatics
- Personal digital assistants, natural language processing, wearable computing and implantable devices
- Global navigation satellite and inertial navigation systems
Design Methods and Tools:
- Design verification and fault tolerance
- Embedded system security and security validation
- System-level design and hardware/software co-design
- High-level synthesis, logic synthesis, communication synthesis
- Embedded real-time systems and real-time operating systems
- Rapid system prototyping, performance analysis and estimation
- Formal models, transformations, algorithm transformations and metrics
Development Platforms, Architectures and Technologies:
- Embedded platforms for multimedia and telecommunication
- Many-core and multi-processor systems, SoCs, and NoCs
- Reconfigurable ASIPs, FPGAs, and dynamically reconfigurable systems
- Memory system and cache management
- Asynchronous (self-timed) circuits and analog and mixed-signal circuits